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1 features ? processor bus frequency up to 66 mhz and 83.3 mhz 64-bit data bus and 32-bit address bus l2 cache control for 256-kbyte, 512-kbyte, 1-mbyte sizes provides support for either asynchronous sram, burst sram or pipelined burst sram compliant with pci specification, revision 2.1 pci interface operates at 20 to 33 mhz, 3.3v/5.0v-compatible ieee 1149.1-compliant, jtag boundary-scan interface p d max = 1.7 watts (66 mhz), full operating conditions nap, doze and sleep modes reduce power consumption fully compliant with mil-std-883 class q or according to atmel standards upscreenings based on atmel standards full military temperature range (-55 c t c +125 c) ? industrial temperature range (-40 c t c +110 c) v cc =3.3v5% available in a 303-ball cbga or a 303-ball cbga with solder column interposer (sci) (ci-cga) package description the tspc106 provides an integrated, high-bandwidth, high-performance, ttl-com- patible interface between a 60x processor, a secondary (l2) cache or up to a total of four additional 60x processors, the pci bus and main memory. pci support allows system designers to rapidly design systems using peripherals already designed for pci. the tspc106 uses an advanced 3.3v cmos-process technology and maintains full interface compatibility with ttl devices. the tspc106 integrates system testability and debugging features via jtag bound- ary-scan capability. g suffix cbga 303 ceramic ball grid array gs suffix cicga 303 ceramic ball grid array with solder column interposer (sci) pci bridge/ memory controller tspc106 rev. 2102b ? hirel ? 02/02
2 tspc106 2102b ? hirel ? 02/02 figure 1. tspc106 block diagram functional description the tspc106 provides a powerpc ? microprocessor chrp-compliant bridge between the powerpc microprocessor family and the pci bus. chrp is a set of specifications that defines a unified personal computer architecture and brings the combined advan- tages of the power macintosh ? platform and the standard pc environment to both system vendors and users. pci support allows system designers to rapidly design sys- tems using peripherals already designed for pci and other standard interfaces available in the personal computer hardware environment. these open specifications make it easier for system vendors to design computers capable of running multiple operating systems. the tspc106 integrates secondary cache control and a high-performance memory controller. the tspc106 uses an advanced 3.3v cmos process technology and is fully compatible with ttl devices. the tspc106 supports a programmable interface to a variety of powerpc microproces- sors operating at select bus speeds. the 60x address bus is 32 bits wide; the data bus is 64 bits wide. the 60x processor interface of the tspc106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. the address and data buses are decoupled to support pipelined transactions. memory interface power management 60x processor interface l2 cache interface error/interrupt control target master configuration registers pci interface memory l2 60x bus pci bus
3 tspc106 2102b ? hirel ? 02/02 the tspc106 provides support for the following configurations of 60x processors and l2 cache: up to four 60x processors with no l2 cache a single 60x processor plus a direct-mapped, lookaside l2 cache using the internal l2 cache controller of the tspc106 up to four 60x processors plus an externally controlled l2 cache (e.g., the motorola mpc2604ga integrated l2 lookaside cache) the memory interface controls processor and pci interactions to main memory and is capable of supporting a variety of configurations using dram, edo, or sdram and rom or flash rom. the pci interface of the tspc106 complies with the pci local bus specification revi- sion 2.1 and follows the guidelines in the pci system design guide revision 1.0 for host bridge architecture. the pci interface connects the processor and memory buses to the pci bus to which i/o components are connected. the pci bus uses a 32-bit mul- tiplexed address/data bus plus various control and error signals. the pci interface of the tspc106 functions as both a master and target device. as a master, the 106 supports read and write operations to the pci memory space, the pci i/o space and the pci configuration space. the tspc106 also supports pci special- cycle and interrupt-acknowledge commands. as a target, the tspc106 supports read and write operations to system memory. the tspc106 provides hardware support for four levels of power reduction: doze, nap, sleep and suspend. the design of the tspc106 is fully static, allowing internal logic states to be preserved during all power saving modes.
4 tspc106 2102b ? hirel ? 02/02 pin description figure 2. tspc106 in 303-ball cbga package 1615141312111098765 4 3 21 w dl26 dl28 dl30 dh31 dh29 dh27 dh25 dh23 dh21 dh19 dh17 dh15 dh13 dh11 dh9 dh7 v dl24 dl27 dl29 dl31 dh30 dh28 dh26 dh24 dh20 dh18 dh16 dh14 dh12 dh10 dh8 dl22 u ma1/ sdba0/ ar9 dl23 dl25 dl14 pll2 pll0 dl12 dl10 dl4 dl2 dl0 doe / dbgl2 dbg1 dh6 dl21 dl20 t ma2/ sdma2/ ar10 we dh0 dl15 pll3 pll1 dl13 dl11 dl3 dl1 tv/ br2 ba0/ br3 hit dirty_in / br1 dl19 dcs / bg3 r ma3/ sdma3/ ar11 rcs0 dh2 dh1 dl16 vss vdd dl9 dl5 vss vdd twe/ bg2 dirty_out / bg1 ads / dale / brl2 a0 ts p ma5/ sdma5/ ar13 ma4/ sdma4/ ar12 dh4 dh3 vss vdd vss dl8 dl6 vdd vss vdd ba1/ baa bgl2 dwe0/ dbg2 a1 xats/ sdma1 n ma6/ sdma6/ ar14 ma0/ sdba1/ sdma0/ ar0 dl17 dh5 vdd vss vdd dl7 dh22 vss vdd vss lbclaim ci a2 ta m ma8/ sdma8/ ar16 ma7/ sdma7/ ar15 ras0/ cs0 dl18 vss vdd vss nc nc vdd vss vdd wt gbl a3 tt4 l hrst ma9/ sdma9/ ar17 qack ras1 / cs1 vdd cko/ dwe2 ras5/ cs5 vss vdd vss sysclk dbg0 tbst br0 a4 tt3 k ma11/ sdma11/ ar19 ma10/ sdma10/ ar18 ras3/ cs3 ras2/ cs2 ras4/ cs4 ras7/ cs7 vdd avdd vss vdd a9 a8 a7 bg0 a5 tt2 j ma12/ sdma12/ ar20 cas0/ dqm0 ppen rcs1 ras6/ cs6 mcp dbglb/ cke vss vdd vss a11 a6 a13 a12 a10 tea h qreq cas1 / dqm1 sus- pend trst vss dwe1 / dbg3 pirq / sdras nc nc vdd vss vdd a15 a14 a16 tt1 g cas2 / dqm2 rtc cas4 / dqm4 cas5 / dqm5 vdd lssd_ mode vdd par lock vss vdd vss tsiz1 tsiz0 a17 tt0 f bctl0 bctl1 cas6 / dqm6 tck vss vdd vss perr dev- sel vdd vss vdd a21 tsiz2 artry a18 e cas3/ dqm3 nmi cas7/ dqm7 mdle/ sdcas tdo vss vdd serr irdy vss vdd a31 a29 a22 a20 a19 d pa r 0 / ar1 pa r 1 / ar2 tms foe ad28 ad24 ad21 ad17 ad14 ad10 c/be0 ad4 ad0 a30 aack a23 c pa r 2 / ar3 pa r 3 / ar4 par 5 / ar6 ad30 ad26 ad23 ad19 c/be2 c/be1 ad12 ad8 ad6 ad2 a27 a25 a24 b pa r 4 / ar5 pa r 7 / ar8 ad1 tdi ad7 ad11 ad15 trdy ad18 ad22 ad25 ad29 req isa_master/ berr a28 a26 a pa r 6 / ar7 gnt ad3 ad5 ad9 ad13 frame stop ad16 ad20 c/be3 ad27 ad31 flshreq memack
5 tspc106 2102b ? hirel ? 02/02 figure 3. pin assignments shading ley pinout nc v ss no connect power supply ground v dd av dd power supply positive clock power supply positive (k9) signals view table 1 . tspc106 pinout in 303-ball cbga package signal name pin number active i/o 60x processor interface signals a[0:31] r2, p2, n2, m2, l2, k2, j5, k4, k5, k6, j2, j6, j3, j4, h3, h4, h2, g2, f1, e1, e2, f4, e3, d1, c1, c2, b1, c3, b2, e4, d3, e5 high i/o aack d2 low i/o artry f2 low i/o bg0 k3 low output bg1 (dirty_out) r4 low output bg2 (twe) r5 low output bg3 (dcs) t1 low output br0 l3 low input br1 (dirty_in) t3 low input br2 (tv) t6 low input br3 (ba0) t5 low input ci n3 low i/o dbg0 l5 low output dbg1 (toe) u4 low output dbg2 (dwe0) p3 low output dbg3 (dwe1) h11 low output dbglb (cke) j10 low output dh[0:31] t14, r13, r14, p13, p14, n13, u3, w1, v2, w2, v3, w3, v4, w4, v5, w5, v6, w6, v7, w7, v8, w8, n8, w9, v9, w10, v10, w11, v11, w12, v12, w13 high i/o dl[0:31] u6, t7, u7, t8, u8, r8, p8, n9, p9, r9, u9, t9, u10, t10, u13, t13, r12, n14, m13, t2, u1, u2, v1, u15, v16, u14, w16, v15, w15, v14, w14, v13 high i/o gbl m3 low i/o lbclaim n4 low input
6 tspc106 2102b ? hirel ? 02/02 mcp j11 low output ta n 1 low i/o tbst l4 low i/o tea j1 low output ts r1 low i/o tsiz[0:2] g3, g4, f3 high i/o tt[0:4] g1, h1, k1, l1, m1 high i/o wt m4 low i/o xats (sdma1) p1 low input l2 cache interface signals ads/dale/brl2 r3 low output ba0 (br3) t5 low output ba1/baa/bgl2 p4 low output dbgl2 /doe u5 low output dcs (bg3) t1 low output dirty_in (br1) t3 low input dirty_out (bg1) r4 low output dwe0 (dbg2) p3 low output dwe1 (dbg3) h11 low output dwe2 (cko) l11 low output hit t4 low input toe (dbg1) u4 low output tv (br2) t6 high i/o twe (bg2) r5 low output memory interface signals bctl [0:1] f16, f15 low output berr (isa_master )b3 low input cas /dqm[0:7] j15, h15, g16, e16, g14, g13, f14, e14 low output cke/dbglb j10 high output foe d13 low output ma0/sdba1/sdma0/ar0 n15 high output sdma1 (xats) p1 high output ma1/sdba0/ar9 u16 high output ma[2:12]/sdma[2:12]/ar[10:2 0] t16, r16, p15, p16, n16, m15, m16, l15, k15, k16, j16 high output mdle /sdcas e13 low output table 1 . tspc106 pinout in 303-ball cbga package (continued) signal name pin number active i/o
7 tspc106 2102b ? hirel ? 02/02 par[0:7]/ar[1:8] d16, d15, c16, c15, b16, c14, a16, b15 high i/o ppen j14 low output ras /cs [0:7] m14, l13, k13, k14, k12, l10, j12, k11 low output rcs0 r15 low i/o rcs1 j13 low output rtc g15 high input sdras (pirq) h10 low output we t15 low output pci interface signals (2) ad[31:0] (2) a4, c13, b5, d12, a5, c12, b6, d11, c11, b7, d10, a7, c10, b8, d9, a8, b10, d8, a11, c7, b11, d7, a12, c6, b12, c5, a13, d5, a14, c4,b14,d4 high i/o c/be [3:0] (2) a6,c9,c8,d6 low i/o devsel f8 low i/o flshreq a3 low input frame a10 low i/o gnt a15 low input irdy e8 low i/o isa_master (berr) b3 low input lock g8 low input memack a2 low output pa r g 9 high i/o perr f9 low i/o pirq (sdras) h10 low output req b4 low output serr e9 low i/o stop a9 low i/o trdy b9 low i/o interrupt, clock and power management signals ck0 (dwe2 ) l11 high output hrst l16 low input nmi e15 high input qack l14 low output qreq h16 low input sysclk l6 clock input suspend h14 low input test/configuration signals table 1 . tspc106 pinout in 303-ball cbga package (continued) signal name pin number active i/o
8 tspc106 2102b ? hirel ? 02/02 notes: 1. some signals have dual functions and are shown more than once in this table. 2. all pci signals are in little-endian bit order. 3. this test signal is for factory use only. it must be pulled up to v dd for normal device operation. signal description the signals on the tspc106 are grouped as follows: 60x processor interface signals l2 cache/multiple processor interface signals memory interface signals pci interface signals interrupt, clock and power management signals ieee 1149.1 interface signals configuration signals note: a bar over a signal name indicates that the signal is active low, for example, address retry (artry ) and transfer start (ts ). active-low signals are referred to as asserted (active) when they are low and negated when they are high. signals that are not active low such as tag valid (tv) and nonmaskable interrupt (nmi) are referred to as asserted when they are high and negated when they are low. note: for multiple-function signals, outlined signal names refer to the alternate function(s) of the signal being described. for example, the l2 controller signal, (tag output enable toe ), has the alternate function data bus grant 1 (dbg1 ) when the tspc106 is config- ured for a second 60x processor. pll[0:3] u11, t11, u12, t12 high input tck f13 clock input tdi b13 high input tdo e12 high output tms d14 high input trst h13 low input power and ground signals av dd k9 high clock lssd_mode (3) g11 low input v dd e10, e6, f11, f5, f7, g10, g12, g6, h5, h7, k10, k7, l12, m11, m5, m7, n10, n12, n6, p11, p5, p7, r10, r6, j8, l8 high power v ss e11, e7, f10, f12, f6, g5, g7, h12, h6, j7, l7, m10, m12, m6, n11, n5, n7, p10, p12, p6, r11, r7, k8, j9, l9 low ground nc h8, h9, m8, m9 ?? table 1 . tspc106 pinout in 303-ball cbga package (continued) signal name pin number active i/o
9 tspc106 2102b ? hirel ? 02/02 figure 4. symbol note: some signals have dual functions and are shown more than once in this figure. a[0:31] ad[31:0] pa r pci interface memory interface interrupt, clock and power management signals configuration 60x processor interface l2 cache/ multiple processor interface ieee 1149.1 jtag interface c/be[3:0] ras[0:7] trdy irdy frame stop lock devsel serr, perr isa_master req gnt flshreq memack pirq cas[0:7] we ma0/ar0 ma[1:12]/ar[9:20] par[0:7]/ar[1:8] foe (1) mdle, ppen rcs1 bctl0, bctl1 rtc sysclk, cko (1) hrst nmi qreq qack suspend dbg0 foe (1) rcs0 (1) rcs0 (1) pll[0:3] 32 4 1 1 1 1 1 1 1 1 1 1 1 2 1 1 8 8 1 1 12 8 1 2 1 1 2 1 2 1 1 1 1 1 1 1 1 4 br0 bg0 ts xats tt[0:4] tsiz[0:2] tbst wt, ci, gbl aack artry dbg0 (1) dh[0:31], dl[0:31] ta lbclaim dbglb mcp, tea ads/dale/brl2 baa/ba1/bgl2 doe/dbgl2 dwe[0:2]/dbg2, dbg3, cko (1) hit dcs/bg3 ba0/br3 twe/bg2 tv/br2 dirty_in/br1 dirty_out/bg1 toe/dbg1 tdo tdi tck tms trst 1 1 1 1 32 5 3 1 1 1 1 64 1 1 1 3 2 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1
10 tspc106 2102b ? hirel ? 02/02 60x processor interface signals table 2 . 60x processor interface signals signal signal name number of pins i/o signal description a[0:31] address bus 32 o specifies the physical address for 60x bus snooping. i specifies the physical address of the bus transaction. for burst reads, the address is aligned to the critical double-word address that missed in the instruction or data cache. for burst writes, the address is aligned to the double-word address of the cache line being pushed from the data cache. aack address acknowledge 1 o indicates that the address tenure of a transaction is terminated. on the cycle following the assertion of aack , the bus master releases the address-tenure-related signals to a high impedance state and samples artry . i indicates that an externally-controlled l2 cache is terminating the address tenure. on the cycle following the assertion of aack ,thebus master releases the address-tenure-related signals to a high impedance state and samples artry . artry address retry 1 o indicates that the initiating 60x bus master must retry the current address tenure. i during a snoop operation, indicates that the 60x either requires the current address tenure to be retried due to a pipeline collision or needs to perform a snoop copy-back operation. during normal 60x bus cycles in a multiprocessor system, indicates that the other 60x or external l2 controller requires the address tenure to be retried. bg0 bus grant 0 1 o indicates that the primary 60x may, with the proper qualification, begin a bus transaction and assume mastership of the address bus. br0 bus request 0 1 i indicates that the primary 60x requires the bus for a transaction. ci cache inhibit 1 i/o indicates that an access is caching-inhibited. dbg0 data bus grant 0 1 o indicates that the 60x may, with the proper qualification, assume mastership of the data bus. dbglb local bus slave data bus grant 1 o indicates that the 60x processor is prepared to accept data and the local bus slave should drive the data bus.
11 tspc106 2102b ? hirel ? 02/02 dh[0:31], dl[0:31] data bus 64 the data bus is comprised of two halves - data bus high (dh[0:31]) and data bus low (dl[0:31]). the data bus has the following byte lane assignments: o represents the value of data being driven by the tspc106. i represents the state of data being driven by a 60x processor, the local bus slave, the l2 cache or the memory subsystem. gbl global 1 i/o indicates that an access is global and hardware needs to enforce coherency. lbclaim local bus slave cycle claim 1 i indicates that the local bus slave claims the transaction and is responsible for driving ta during the data tenure. mcp machine check 1 o indicates that the tspc106 detected a catastrophic error and the 60x processor should initiate a machine check exception. ta transfer acknowledge 1 o indicates that the data has been latched for a write operation or that the data is valid for a read operation, thus terminating the current data beat. if it is the last (or only) data beat, this also terminates the data tenure. i indicates that the external l2 cache or local bus slave has latched data for a write operation or is indicating the data is valid for a read operation. if it is the last (or only) data beat, then the data tenure is terminated. tbst transfer burst 1 o indicates that a burst transfer is in progress. i indicates that a burst transfer is in progress. tea transfer error acknowledge 1 o indicates that a bus error has occurred. assertion of tea terminates the transaction in progress. an unsupported memory transaction, such as a direct-store access or a graphics read or write, causes the assertion of tea (provided tea is enabled). ts transfer start 1 o indicates that the tspc106 has started a bus transaction and that the address and transfer attribute signals are valid. note that the tspc106 only initiates a transaction to broadcast the address of a pci access to memory for snooping purposes. i indicates that a 60x bus master has begun a transaction and that the address and transfer attribute signals are valid. table 2 . 60x processor interface signals (continued) signal signal name number of pins i/o signal description data byte byte lane dh[0:7] 0 dh[8:15] 1 dh[16:23] 2 dh[24:31] 3 dl[0:7] 4 dl[8:15] 5 dl[16:23] 6 dl[24:31] 7
12 tspc106 2102b ? hirel ? 02/02 l2 cache/multiple processor interface signals the tspc106 provides support for either an internal l2 cache controller or an external l2 cache controller and/or additional 60x processors. internal l2 controller signals table 3 lists the interface signals for the internal l2 controller and provides a brief description of their functions. the internal l2 controller supports either burst srams or asynchronous srams. some of the signals perform different functions depending on the sram configuration. tsiz[0:2] transfer size 3 o specifies the data transfer size for the 60x bus transaction. i specifies the data transfer size for the 60x bus transaction. tt[0:4] transfer type 5 o specifies the type of 60x bus transfer in progress. i specifies the type of 60x bus transfer in progress. wt write-through 1 i/o indicates that an access is write-through. xats extended address transfer start 1 i indicates that the 60x has started a direct-store access (using the extended transfer protocol). since direct-store accesses are not supported by the tspc106, the tspc106 automatically asserts when tea and xats are asserted (provided tea is enabled). table 2 . 60x processor interface signals (continued) signal signal name number of pins i/o signal description table 3 . internal l2 controller signals signal signal name number of pins i/o signal description ads dale brl2 address strobe 1 o for a burst sram configuration, indicates to the burst sram that the address is valid to be latched. ba0 br3 burst address 0 1 i/o for an asynchronous sram configuration, indicates bit 0 of the burst address counter. ba1 baa bgl2 burst address 1 1 o for an asynchronous sram configuration, indicates bit 1 of the burst address counter. baa ba1 bgl2 bus address advance 1 o for a burst sram configuration, indicates that the burst rams should increment their internal addresses. dale ads brl2 data address latch enable 1 o for an asynchronous sram configuration, indicates that the external address latch should latch the current 60x bus address. dcs bg3 data ram chip select 1 o enables the l2 data rams for a read or write operation. dirty_in br1 dirty in 1 i indicates that the selected l2 cache line is modified. the polarity of dirty_in is programmable. dirty_out bg1 dirty out 1 o indicates that the l2 cache line should be marked as modified. the polarity of dirty_out is programmable.
13 tspc106 2102b ? hirel ? 02/02 external l2 controller signals when an external l2 cache controller is used instead of the internal l2 cache controller, four signals change their functions. doe dbgl2 data ram output enable 1 o indicates that the l2 data rams should drive the data bus. dwe[0:2] dbg2 dbg3 data ram write enable 3 o indicates that a write to the l2 data rams is in progress. multiple pins are provided to reduce loading. hit hit 1 i indicates that the l2 cache has detected a hit. the polarity of hit is programmable. toe dbg1 tag output enable 1 o indicates that the tag ram should drive the l2 tag address onto the address bus. tv br2 tag valid 1 i/o indicates that the current l2 cache line should be marked valid. the polarity of tv is programmable. twe bg2 tag write enable 1 o indicates that the l2 tag address, valid, and dirty bits should be updated. table 3 . internal l2 controller signals (continued) signal signal name number of pins i/o signal description table 4 . external l2 controller signals signal signal name number of pins i/o signal description bgl2 ba1 baa external l2 bus grant 1 o indicates that the external l2 controller has been granted mastership of the 60x address bus. brl2 ads dale external l2 bus request 1 i indicates that the external l2 controller requires mastership of the 60x bus for a transaction. dbgl2 doe external l2 data bus grant 1 o indicates that the external l2 controller has been granted mastership of the 60x data bus. hit external l2 hit 1 i indicates that the current transaction is claimed by the external l2 controller. the external l2 controller will assert aack and ta for the transaction.
14 tspc106 2102b ? hirel ? 02/02 multiple processor signals when a system implementation uses more than one 60x processor, nine of the internal l2 cache controller signals change their functions. note that in a multi-processor system, with the exception of the bus grant, bus request and data bus grant signals, all of the 60x processor interface signals are shared by all 60x processors. table 5 . multiple processor signals signal signal name number of pins i/o signal description bg1 dirty_out bus grant 1 1 o indicates that processor 1 may, with the proper qualification, begin a 60x bus transaction and assume mastership of the address bus. bg2 twe bus grant 2 1 o indicates that processor 2 may, with the proper qualification, begin a 60x bus transaction and assume mastership of the address bus. bg3 dcs bus grant 3 1 o indicates that processor 3 may, with the proper qualification, begin a 60x bus transaction and assume mastership of the address bus. br1 dirty_in bus request 1 1 i indicates that processor 1 requires mastership of the 60x bus for a transaction. br2 tv bus request 2 1 i indicates that processor 2 requires mastership of the 60x bus for a transaction. br3 ba0 bus request 3 1 i indicates that processor 3 requires mastership of the 60x bus for a transaction. dbg1 toe data bus grant 1 1 o indicates that processor 1 may, with the proper qualification, assume mastership of the 60x data bus. dbg2 dwe0 data bus grant 2 1 o indicates that processor 2 may, with the proper qualification, assume mastership of the 60x data bus. dbg3 dwe1 data bus grant 3 1 o indicates that processor 3 may, with the proper qualification, assume mastership of the 60x data bus.
15 tspc106 2102b ? hirel ? 02/02 memory interface signals table 6 lists the memory interface signals and provides a brief description of their func- tions. the memory interface supports either standard drams or edo drams, and either standard roms or flash roms. some of the memory interface signals perform different functions depending on the ram and rom configurations. table 6 . memory interface signals signal signal name number of pins i/o signal description ar0 ma0 rom address 0 8 o represents address bit 0 of the 8-bit rom/flash. note that ar0 is only supported for rom bank 0 when configured for an 8-bit rom/flash data bus width. the extra address bit allows for up to 2 mbytes of rom when using the 8-bit wide data path. bits 1 - 8 of the rom address are provided by ar[1:8] and bits 9 - 20 of the rom address are provided by ar[9:20]. ar[1:8] par[0:7] rom address 1 - 8 8 o represents bits 1 - 8 of the rom/flash address. the other rom address bits are provided by ar0 and ar[9:20]. ar[9:20] ma[1:12] rom address 9-20 12 o represents bits 9 - 20 of the rom/flash address (the 12 lowest order bits, with ar20 as the least significant bit (lsb)). bits 0 - 8 of the rom address are provided by ar0 and ar[1:8]. bctl [0:1] buffer control 0 - 1 2 o used to control external data bus buffers (directional control and high- impedance state) between the 60x bus and memory. note that external data buffers may be optional for lightly loaded data buses, but buffers are required whenever an l2 cache and rom/flash (on the 60x/memory bus) are both in the system or when ecc is used. cas [0:7] column address strobe0-7 8 o indicates a memory column address is valid and selects one of the columns in the row. cas0 connects to the most significant byte select. cas7 connects to the least significant byte select. foe flash output enable 1 o enables flash output for the current read access. ma0 ma[1:12] ar0 ar[9:20] memory address 0-12 13 o represents the row/column multiplexed physical address for drams or edos (ma0 is the most significant address bit; ma12 is the least significant address bit). note that ma0 also functions as the rom address signal ar0 and ma[1:12] function as the rom address signals ar[9:20]. mdle memory data latch enable 1 o enables the external, latched data buffer for read operations, if such a buffer is used in the system. par[0:7] ar[1:8] data parity/ecc 8 o represents the byte parity or ecc being written to memory (par0 is the most significant bit). i represents the byte parity or ecc being read from memory (par0 is the most significant bit). ppen parity path read enable 1 o enables external parity/ecc bus buffer or latch for memory read operations. ras [0:7] row address strobe0-7 8 o indicates a memory row address is valid and selects one of the rows in the bank. rcs0 rom/flash bank 0 select 1 o selects rom/flash bank 0 for a read access or flash bank 0 for a read or write access. rcs1 rom/flash bank 1 select 1 o selects rom/flash bank 1 for a read access or flash bank 1 for a read or write access. rtc real-time clock 1 i external clock source for the memory refresh logic when the tspc106 is in the suspend power-saving mode. we write enable 1 o enables writing to dram, edo or flash.
16 tspc106 2102b ? hirel ? 02/02 pci interface signals table 7 lists the pci interface signals and provides a brief description of their functions. note that the bits in table 7 are referenced in little-endian format. the pci specification defines a sideband signal as any signal, not part of the pci speci- fication, that connects two or more pci-compliant agent, and has meaning only to those agents. the tspc106 implements four pci sideband signals -flshreq , isa_master , memack and pirq . table 7 . pci interface signals signal signal name number of pins i/o signal description ad[31:0] address/data 32 i/o represents the physical address during the address phase of a transaction. during the data phase(s) of a pci transaction, ad[31:0] contain data. ad[7:0] define the least significant byte and ad[31:24] the most significant byte. c/be [3:0] command/byte enable 4 o during the address phase, c/be [3:0] define the pci bus command. during the data phase, c/be [3:0] are used as byte enables. byte enables determine which byte lanes carry meaningful data. c/be0 applies to the least significant byte. i during the address phase, c/be [3:0] indicates the pci bus command that another master is sending. during the data phase c/be [3:0] indicate which byte lanes are valid. devsel device select 1 o indicates that the tspc106 has decoded the address and is the target of the current access. i indicates that some pci agent (other than the tspc106) has decoded its address as the target of the current access. flshreq flush request 1 i indicates that a device needs to have the tspc106 flush all of its current operations. frame frame 1 o indicates that the tspc106, acting as a pci master, is initiating a bus transaction. i indicates that another pci master is initiating a bus transaction. gnt pci bus grant 1 i indicates that the tspc106 has been granted control of the pci bus. note that gnt is a point-to-point signal. every master has its own gnt signal. irdy initializer ready 1 o indicates that the tspc106, acting as a pci master, can complete the current data phase of a pci transaction. during a write, the tspc106 asserts irdy to indicate that valid data is present on ad[31:0]. during a read, the tspc106 asserts irdy to indicate that it is prepared to accept data. i indicates another pci master is able to complete the current data phase of the transaction. isa_ master isa master 1 i indicates that an isa master is requesting system memory. lock lock 1 i indicates that a master is requesting exclusive access to memory, which may require multiple transactions to complete. memack memory acknowledge 1 o indicates that the tspc106 has flushed all of its current operations and has blocked all 60x transfers except snoop copy-back operations. the tspc106 asserts memack in response to assertion of flshreq after the flush is complete.
17 tspc106 2102b ? hirel ? 02/02 par parity 1 o asserted indicates odd parity across the ad[31:0] and c/be [3:0] signals during address and data phases. negated indicates even parity. i asserted indicates odd parity driven by another pci master or the pci target during read data phases. negated indicates even parity. perr parity error 1 o indicates that another pci agent detected a data parity error. i indicates that another pci agent detected a data parity error. pirq modified memory interrupt request 1 o in emulation mode (see ? address maps ? on page 19), indicates that a pci write has occurred to system memory that has not been recorded by software. req pci bus request 1 o indicates that the tspc106 is requesting control of the pci bus to perform a transaction. note that req is a point-to-point signal. every master has its own req signal. serr system error 1 o indicates that an address parity error or some other system error (where the result will be a catastrophic error) was detected. i indicates that another target has detected a catastrophic error. stop stop 1 o indicates that the tspc106, acting as the pci target, is requesting that the pci bus master stop the current transaction. i indicates that some other pci agent is requesting that the pci initiator stop the current transaction. trdy target ready 1 o indicates that the tspc106, acting as a pci target, can complete the current data phase of a pci transaction. during a read, the tspc106 asserts trdy to indicate that valid data is present on ad[31:0]. during a write, the tspc106 asserts trdy to indicate that it is prepared to accept data. i indicates that another pci target is able to complete the current data phase of a transaction. table 7 . pci interface signals signal signal name number of pins i/o signal description
18 tspc106 2102b ? hirel ? 02/02 interrupt, clock and power management signals the tspc106 coordinates interrupt, clocking, and power management signals across the memory bus, the pci bus and the 60x processor bus. ieee 1149.1 interface signals to facilitate system testing, the tspc106 provides a jtag test access port that complies with the ieee 1149.1 boundary- scan specification. table 8 . interrupt, clock and power management signals signal signal name number of pins i/o signal description cko dwe2 test clock 1 o cko provides a means to monitor the internal pll output or the bus clock frequency. the cko clock should be used for testing purposes only. it is not intended as a reference clock signal. hrst hard reset 1 i initiates a complete hard reset of the tspc106. during assertion, all bi-directional signals are released to a high-impedance state and all output signals are either in a high impedance or inactive state. nmi nonmaskable interrupt 1 i indicates that an external device (typically an interrupt controller) has detected a catastrophic error. in response, the tspc106 asserts mcp on the 60x processor bus. qack quiesce acknowledge 1 o indicates that the tspc106 is in a low-power state. all bus activity that requires snooping has terminated and the 60x processor may enter a low-power state. qreq quiesce request 1 i indicates that a 60x processor is requesting that all bus activity involving snoop operations pause or terminate so that the 60x processor may enter a low-power state. suspend suspend 1 i activates the suspend power-saving mode. sysclk system clock 1 i sysclk sets the frequency of operation for the pci bus and provides a reference clock for the phase-locked loop (pll) in the tspc106. sysclk is used to synchronize bus operations. refer to section ? clocking ? on page 19 for more information. table 9 . ieee 1149.1 interface signals signal signal name number of pins i/o signal description tck jtag test clock 1 i input signals to the test access port (tap) are clocked in on the rising edge of tck. changes to the tap output signals occur on the falling edge of tck. the test logic allows tck to be stopped. tdo jtag test data output 1 o the contents of the selected internal instructions or data register are shifted out onto this signal on the falling edge of tck. tdo will remain in a high-impedance state except when scanning of data is in progress. tdi jtag test data input 1 i the value presented on this signal on the rising edge of tck is clocked into the selected jtag test instruction or data register. tms jtag test mode select 1 i this signal is decoded by the internal jtag tap controller to distinguish the primary operation of the test support circuitry. trst jtag test reset 1 i this input causes asynchronous initialization of the internal jtag tap controller.
19 tspc106 2102b ? hirel ? 02/02 configuration signals the configuration signals select the rom/flash options, the clock mode of the tspc106 and how the tspc106 responds to addresses on the 60x and pci buses. notes: 1. the tspc106 samples these signals during a power-on reset or hard reset operation to determine the configuration. weak pull-up or pull-down resistors should be used to avoid interference with the normal signal operations. 2. the tspc106 continuously samples the phase-locked loop (pll) configuration signals to allow the switching of clock modes or the bypass of the pll without a hard reset operation. clocking the tspc106 requires a single system clock input, sysclk. the frequency of sysclk dictates the operating frequency of the pci bus. an internal pll on the tspc106 generates a master clock that is used for all of the internal (core) logic. the master clock provides the core frequency reference and is phase-locked to the sysclk input. the 60x processor, l2 cache and memory interfaces operate at the core frequency. the pll[0:3] signals configure the core-to-sysclk frequency ratio. the tspc106 sup- ports core-to-sysclk frequency ratios of 1:1, 2:1 and 3:1, although not all ratios are supported for all frequencies. the tspc106 supports changing the clock mode and bypassing the pll without requiring a hard reset operation, provided the system design allows sufficient time for the pll to relock. address maps the tspc106 supports three address mapping configurations designated address map a, address map b, and emulation mode address map. address map a conforms to the ? powerpc reference platform specification ? . address map b conforms to the ? pow- erpc common hardware reference platform architecture (chrp) ? . the emulation mode address map is provided to support software emulation fx86 hardware. the con- figuration signal dbg0 , sampled during power-on reset, selects between address map a and address map b. after reset, the address map can be changed by a programmable parameter. the emulation mode address map can only be selected by software after reset. table 1 0. configuration signals signal number of pins i/o configuration dbg0 (1) 1 i high configures the tspc106 for address map a. low configures the tspc106 for address map b. foe (1) 1 i high configures rom bank 0 for an 8-bit data bus width. low configures rom bank 0 for an 64-bit data bus width. note that the data bus width for rom bank 1 is always 64 bits. pll[0:3] (2) 4 i high/low ? configuration for the pll clock mode. rcs0 (1) 1 i high indicates rom is located on the 60x processor/memory data bus. low indicates rom is located on the pci bus.
20 tspc106 2102b ? hirel ? 02/02 detailed specifications scope this drawing describes the specific requirements of the tspc106 in compliance with mil-std-883 class b or manufacturer ? s standard screening. applicable documents documents applicable to the information contained in this datasheet are: 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535: general specifications for microcircuits requirements general the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections the terminal connections are as shown in ? pin description ? on page 4. lead material and finish lead material and finish are as specified in ? package mechanical data ? on page 37. package the macrocircuits are packaged in 303-pin ceramic ball grid array packages. the precise package drawings are described at the end of the specification. ? cbga package parameters ? on page 37 and ? ci_cga package parameters ? on page 38. absolute maximum ratings stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. notes: 1. functional operating conditions are given in ac and dc electrical specifications. stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. 2. caution: input voltage must not be greater than the v dd supply voltage by more than 2.5v at all times including during power-on reset. thermal characteristics this section provides thermal management information for the c4/cbga package. proper thermal control design is primarily dependent upon the system-level design. the use of c4 die on cbga interconnect technology offers significant reduction in both the signal delay and the microelectronic packaging volume. figure 5 shows the salient features of the c4/cbga interconnect technology. the c4 interconnection provides both the electrical and the mechanical connections for the die to the ceramic substrate. table 11. absolute maximum ratings symbol parameter min max unit v dd supply voltage -0.3 3.6 v av dd pll supply voltage -0.3 3.6 v v in input voltage -0.3 5.5 v t stg storage temperature range -55 +150 c
21 tspc106 2102b ? hirel ? 02/02 after the c4 solder bump is reflowed, epoxy (encapsulant) is under-filled between the die and the substrate. under-fill material is commonly used on large high-power die; however, this is not a requirement of the c4 technology. the package substrate is a multilayer-co-fired ceramic. the package-to-board interconnection is via an array of orthogonal 90/10 (lead/tin) solder balls on 1.27 mm pitch. during assembly of the c4/cbga package to the board, the high-melt balls do not collapse. figure 5. exploded cross-section internal package conduction resistance for the c4/cbga packaging technology, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case thermal resistance the die junction-to-lead thermal resistance these parameters are shown in table 12. in the c4/cbga package, the silicon chip is exposed; therefore, the package case is the top of the silicon. figure 6 shows a simplified thermal network in which a c4/cbga package is mounted on a printed-circuit board. figure 6. c4/cbga package mounted on a printed circuit board note: internal package resistance differs from external package resistance. cbga package ci_cga package chip with c4 encapsulant ceramic substrate bga joint printed circuit board table 12. thermal resistance thermal metric effective thermal resistance junction-to-case thermal resistance 0.133 c/w junction-to-lead (ball) thermal resistance 3.8 c/w (cbga package) junction-to-lead (column) thermal resistance 4.0 c/w (ci_cga package) external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed circuit board radiation convection
22 tspc106 2102b ? hirel ? 02/02 power consumption the tspc106 provides hardware support for four levels of power reduction ? the doze, nap and sleep modes are invoked by register programming and the suspend mode is invoked by assertion of an external signal. the design of the tspc106 is fully static, allowing internal logic states to be preserved during all power-saving modes. the follow- ing sections describe the programmable power modes provided by the tspc106. full-power mode this is the default power state of the tspc106 following a hard reset with all internal functional units fully powered and operating at full clock speed. doze mode in this power-saving mode, all the tspc106 functional units are disabled except for pci address decoding, system ram refreshing and 60x bus request monitoring (through br n ). once the doze mode is entered, a hard reset, a pci transaction referenced to system memory or a 60x bus request can bring the tspc106 out of the doze mode and into the full-on state. if the tspc106 is awakened for a processor or pci bus access, the access is completed and the mc106 returns to the doze mode. the tspc106 ? s doze mode is totally independent of the power saving mode of the processor. nap mode nap mode provides further power savings compared to doze mode. in nap mode, both the processor and the tspc106 are placed in a power reduction mode. in this mode, only the pci address decoding, system ram refresh and the processor bus request monitoring are still operating. hard reset, a pci bus transaction referenced to system memory or a 60x bus request can bring the tspc106 out of the nap mode. if the tspc106 is awakened by a pci access, the access is completed and the tspc106 returns to the nap mode. if the tspc106 is awakened by a processor access, the access is completed but the tspc106 remains in the full-on state. when in the nap mode, the pll is required to be running and locked to the system clock (sysclk). sleep mode sleep mode provides further power saving compared to the nap mode. as in nap mode, both the processor and the tspc106 are placed in a reduced power mode concurrently. in sleep mode, no functional units are operating except the system ram refresh logic, which can continue (optionally) to perform the refresh cycles. a hard reset or a bus request wakes the tspc106 from sleep mode. the pll and sysclk inputs may be disabled by an external power management controller (pmc). for additional power sav- ings, the pll can be disabled by configuring the pll[0:3] signals into the pll-bypass mode. the external pmc must enable the pll, turn on sysclk and allow the pll time to lock before waking the system from sleep mode. suspend mode suspend mode is activated through assertion of the suspend signal. in suspend mode, the tspc106 may have its clock input and pll shut down for additional power savings. memory refresh can be accomplished in two ways, either by using self-refresh mode drams or by using the rtc input on the tspc106. to exit the suspend mode, the system clock must be turned on in sufficient time to restart the pll. after this time, suspend may be negated. in suspend mode, all outputs (except memory refresh) are released to a high-impedance state and all inputs, including hard reset (hrst ), are ignored.
23 tspc106 2102b ? hirel ? 02/02 power dissipation table 13 provides figures on power consumption for the tspc106. notes: 1. power consumption for common system configurations assuming 50 pf loads. 2. suspend power saving mode assumes sysclk off and pll in bypass mode. 3. typical power is an average value measured at v dd =av dd =3.30vandt a =25 c. 4. maximum power is measured at v dd =av dd =3.45vandt a =25 c. marking the documents that define the marking are identified in the related reference docu- ments. each microcircuit is legibly and permanently marked with the following information as a minimum: manufacturer logo manufacturer part number class b identification (if applicable) date-code of inspection lot esd identifier (if available) country of manufacture table 13. power consumption mode sysclk/core33/66 mhz sysclk/core33/83.3 mhz unit full-on mode typical 1.2 2.2 w maximum 1.4 2.4 w doze mode typical 1.0 1.1 w maximum 1.2 1.4 w nap mode typical 1.0 1.1 w maximum 1.2 1.4 w sleep mode typical 260 330 w maximum 360 450 w suspend mode typical 140 220 w maximum 190 270 w
24 tspc106 2102b ? hirel ? 02/02 electrical characteristics general requirements all static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given in table 15. notes: 1. excludes test signals (lssd_mode and jtag signals). 2. this value represents worst case 40 ohm drivers (default value for processor/l2 control signals ci ,wt ,gbl , tbst ,tsiz[0- 2], tt[0-4], twe , and tv ) only. other signals have lower default driver impedance and will support larger i oh and i ol .all drivers may optionally be programmed to different driver strengths. 3. capacitance is periodically sampled rather than 100% tested. table 1 4. recommended operating conditions characteristic symbol value unit notes supply voltage v dd 3.3 165 mv v pll supply voltage av dd min 2.51 - max 3.465 v input voltage v in 0to5.5 v die junction temperature t j 0to105 c the extended temperature parts have die junction temperature of -40 to 105 c table 1 5. clock dc timing specifications (v dd = 3.3v 5% dc, gnd = 0v dc, -55 c t c 125 c) symbol characteristic min max unit v ih input high voltage (all inputs except sysclk) 2 5.5 v v il input low voltage (all inputs except sysclk) gnd 0.8 v cv ih sysclk input high voltage 2.4 5.5 v cv il sysclk input low voltage gnd 0.4 v i in input leakage current, v in =3.3v (1) 15.0 a i tsi hi-z (off-state) leakage current, v in =3.3v (1) 15.0 a v oh output high voltage, i oh =-7ma 2.4 v v ol output low voltage, i ol =7ma 0.5 v v oh pci 3.3v signaling output high voltage, i oh =-0.5ma 2.7 v v ol pci 3.3v signaling output low voltage, i ol =1.5ma 0.3 v c in capacitance, v in =0v,f=1mhz (2) 7.0 pf
25 tspc106 2102b ? hirel ? 02/02 dynamic characteristics this section provides the ac electrical characteristics for the tspc106. after fabrica- tion, parts are sorted by maximum 60x processor bus frequency as shown in table 16 and tested for conformance to the ac specifications for that frequency. these specifica- tions are for operation between 16.67 and 33.33 mhz pci bus ( sysclk) frequencies. the 60x processor bus frequency is determined by the pci bus (sysclk) frequency and the settings of the pll[0:3] signals. all timings are specified relative to the rising edge of sysclk. clock ac specifications table 16 provides the clock ac timing specifications as defined in figure 7. notes: 1. the sysclk frequency and pll[0:3] settings must be chosen so that the resulting sysclk (bus) frequency, cpu (core) frequency and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll[0:3] signal description in ? system design information ? on page 33 for valid pll[0:3] settings. 2. rise and fall times for the sysclk input are measured from 0.4v to 2.4v. 3. timing is guaranteed by design and characterization and is not tested. 4. the total input jitter (short-term and long-term combined) must be under 200 ps. 5. pll-relock time is the maximum time required for pll lock after a stable v dd ,av dd , and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently reenabled dur- ing the sleep and suspend power-saving modes. also note that hrst must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 ms) during the power-on reset sequence. figure 7. sysclk input timing diagram note: vm = midpoint voltage (1.4v) table 1 6. clock ac timing specifications (v dd = 3.3v 5% dc, gnd = 0v dc, -55 c t c 125 c) ref characteristic sysclk/core 33/66 mhz sysclk/core 33/83.3 mhz unit min max min max 60x processor bus (core) frequency (1) 16.67 66 16.67 83.3 mhz vco frequency (1) 150 400 150 400 mhz sysclk frequency (1) 16.67 33.33 16.67 33.33 mhz 1 sysclk cycle time 30.0 60.0 30.0 60.0 ns 2, 3 sysclk rise and fall time (2) 2.0 2.0 ns 4 sysclk duty cycle measured at 1.4v (3) 40 60 40 60 % sysclk jitter (4) 200 200 ps 106 internal pll relock time (3, 5) 100 100 s sysclk vm vm vm cvil cvih 1 2 3 4 4
26 tspc106 2102b ? hirel ? 02/02 input ac specifications table 17 provides the input ac timing specifications as shown in figure 8 and figure 9. notes: 1. input specifications are measured from the ttl level (0.8 or 2.0v) of the signal in question to the 1.4v of the rising edge of the input sysclk. input and output timings are measured at the pin. 2. processor and memory interface signals are specified from the rising edge of the 60x bus clock. 3. group i input signals include the following processor, l2 and memory interface signals: a[0:31], par[0:7]/ar[1:8],br [0:4], brl2 ,xats ,lbclaim ,ads ,ba0,tvandhit (when configured for external l2). 4. group ii input signals include the following processor and memory interface signals: tbst , tt[0:4], tsiz[0:2], wt ,ci ,gbl , aack and ta . 5. group iii input signals include the following processor and memory interface signals: dl[0:31] and dh[0:31]. 6. group iv input signals include the following processor and l2 interface signals: ts ,artry ,dirty_in and hit (when con- figured for internal l2 controller). 7. pci 3.3 v signaling environment signals are measured from 1.65v (v dd 2) on the rising edge of sysclk to v oh =3.0vor v ol =0.3v. pci 5v signaling environment signals are measured from 1.65v (v dd 2) on the rising edge of sysclk to v oh =2.4vorv ol = 0.55v. 8. group v input signals include the following bussed pci interface signals: frame ,c/be [0:3], ad[0:31], devsel ,irdy , trdy ,stop ,par ,perr , serr ,lock , flshreq , and isa_master . 9. group vi input signal is the point-to-point pci gnt input signal. 10. the setup and hold time is with respect to the rising edge of hrst . mode select inputs include the rcs0 ,foe and dbg0 configuration inputs. 11. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). when the unit is given as t sysclk the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 12. these values are guaranteed by design and are not tested. table 1 7. input ac timing specifications (v dd =3.3v5%dc,gnd=0vdc,c l =50pf,-55 c t c 125 c) ref characteristic 66 mhz 83.3 mhz unit min max min max 10a group i input signals valid to sysclk (input setup) (1,2,3) 4.0 3.5 ns 10a group ii input signals valid to sysclk (input setup) (1,2,4) 3.5 3.5 ns 10a group iii input signals valid to sysclk (input setup) (1,2,5) 3.0 2.5 ns 10a group iv input signals valid to sysclk (input setup) (1,2,6) 5.0 4.0 ns 10b group v input signals valid to sysclk (input setup) (7, 8) 7.0 7.0 ns 10b group vi input signals valid to sysclk (input setup) (7, 9) 7.0 7.0 ns 11a 60x bus clock to group i - iv inputs invalid (input hold) (3,4,5,6) 00ns 11b sysclk to group v - vi inputs invalid (input hold) (8, 9) -0.5 -0.5 ns hrst pulsewidth 255xt sysclk +100 s 255 x t sysclk +100 s 10c mode select inputs valid to hrst (input setup) (10, 11, 12) 3xt sysclk 3xt sysclk ns 11c hrst to mode select input invalid (input hold) (10, 12) 1.0 1.0 ns
27 tspc106 2102b ? hirel ? 02/02 figure 8. input timing diagram note: vm = midpoint voltage (1.4v) figure 9. mode select input timing diagram note: vm = midpoint voltage (1.4v) sysclk vm all inputs 10a 10b 11a hrst vm mode pins 10c 11c
28 tspc106 2102b ? hirel ? 02/02 output ac specifications table 18 provides the output ac timing specifications as shown in figure 10. notes: 1. processor and memory interface signals are specified from the rising edge of the 60x bus clock. 2. output specifications are measured from 1.4v on the rising edge of sysclk to the ttl level (0.8v or 2.0v) of the signal in question. both input and output timings are measured at the pin. 3. the maximum timing specification assumes c l =50pf. 4. the shared outputs ts and artry require pull-up resistors to hold them negated when there is no bus master driving them. 5. when the tspc106 is configured for asynchronous l2 cache srams, the dwe[0:2] signals have a maximum sysclk to output valid time of (0.5 x t proc ) + 8.0 ns (where t proc is the 60x bus clock cycle time). 6. pci 3.3v signaling environment signals are measured from 1.65v (v dd 2) on the rising edge of sysclk to v oh =3.0vor v ol =0.3v. 7. the minimum timing specification assumes c l =50pf. 8. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). when the unit is given as t sysclk ,thenum- bers given in the table must be multiplied by the period of sysclk to compute the actual duration in nanoseconds of the parameter in question. 9. these values are guaranteed by design and are not tested. 10. pci devices which require more than the pci-specified hold time of t h = 0 ns or systems where clock skew approaches the pci-specified allowance of 2 ns may not work with the tspc106. for workarounds, see motorola application note ? design- ing pci 2.1-compliant mpc106 systems ? (order number an1727/d). table 1 8. output ac timing specifications (v dd = 3.3v 5% dc, gnd = 0v dc, c l =50pf,-55 c t c 125 c) ref characteristic 66 mhz 83.3 mhz unit min max min max 12 sysclk to output driven (output enable time) (9) 2.0 2.0 ns 13a sysclk to output valid (for ts and artry ) (1,2,3,4) 7.0 6.0 ns 13b sysclk to output valid (for all non-pci signals except ts ,artry ,ras [0:7] and cas [0:7]) and dwe[0:2] (1,2,3,5) 7.0 6.0 ns 14a sysclk to output valid (for ras[0:7] and cas[0:7]) (1, 2, 3) 7.0 6.0 ns 14b sysclk to output valid (for pci signals) (3, 6) 11.0 11.0 ns 15a sysclk to output invalid for all non-pci signals (output hold) (7, 10) 1.0 1.0 ns 15b sysclk to output valid for pci signals (output hold) (7) 1.0 1.0 ns 18 sysclk to artry high impedance before precharge (output hold) (9) 8.0 8.0 ns 19 sysclk to artry precharge enable (8, 9) (0.4 x t sysclk ) +2.0 (0.4 x t sysclk ) +2.0 ns 21 sysclk to artry high impedance after precharge (8, 9) (1.5 x t sysclk ) +8.0 (1.5 x t sysclk ) +8.0 ns
29 tspc106 2102b ? hirel ? 02/02 figure 10. output timing diagram note: vm = midpoint voltage (1.4v) notes: 1. these values are guaranteed by design, and are not tested. 2. trst is an asynchronous signal. the setup time is for test purposes only. 3. non-test signal input timing with respect to tck. 4. non-test signal output timing with respect to tck. table 1 9. jtag ac timing specifications (independent of sysclk) (v dd = 3.3v 5% dc, gnd = 0v dc,c l =50pf, -55 c t c 125 c) ref characteristic min max unit 1 tck frequency of operation 0 25 mhz tck cycle time 40 ns 2 tck clock pulse width measured at 1.4 v 20 ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck rising edge (1) 10 ns 5 trst assert time 10 ns 6 boundary-scan input data setup time (2) 5ns 7 boundary-scan input data hold time (2) 15 ns 8 tck to output data valid (3) 030ns 9 tck to output high impedance (3) 030ns 10 tms, tdi data setup time 5 ns 11 tms, tdi data hold time 15 ns 12 tck to tdo data valid 0 15 ns 13 tck to tdo high impedance 0 15 ns sysclk vm 14 vm vm 12 16 13 13 15 16 21 20 19 18 all outputs (except ts and artry) ts artry 15
30 tspc106 2102b ? hirel ? 02/02 figure 11. jtag clock input timing diagram figure 12. trst timing diagram figure 13. boundary-scan timing diagram vm 3 3 1 22 vm vm tck tck trst 5 4 tck 8 8 9 input data valid output data valid output data valid 67 data inputs data outputs data outputs data outputs
31 tspc106 2102b ? hirel ? 02/02 figure 14. test access port timing diagram architectural overview 60x processor interface the tspc106 supports a programmable interface to a variety of powerpc microproces- sors operating at select bus speeds.the address bus is 32 bits wide and the data bus is 64 bits wide. the 60x processor interface of the tspc106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. the address and data buses are decoupled to support pipelined transactions. two signals on the tspc106, local bus slave claim (lbclaim ) and data bus grant local bus slave (dbglb ), are provided for an optional local bus slave. however, the local bus slave must be capable of generating the transfer acknowledge (ta ) signal to interact with the 60x processor(s). depending on the system implementation, the processor bus may operate at the pci bus clock rate or at two or three times the pci bus clock rate. the 60x processor bus is synchronous with all timing relative to the rising edge of the 60x bus clock. secondary (l2) cache/multiple processor interface the 106 provides support for the following configurations of 60x processors and l2 cache: up to four 60x processors with no l2 cache a single 60x processor plus a direct-mapped, lookaside, l2 cache using the internal l2 cache controller of the tspc106 up to four 60x processors plus an externally-controlled l2 cache the internal l2 cache controller generates the arbitration and support signals necessary to maintain a write-through or write-back l2 cache. the internal l2 cache controller sup- ports either asynchronous srams, pipelined burst srams or synchronous burst srams, using byte parity for data error detection. tck 12 12 13 input data valid output data valid output data valid 10 11 tdi, tms tdo tdo tdo
32 tspc106 2102b ? hirel ? 02/02 when more than one 60x processor is used, nine signals of the l2 interface change their functions (to br [1:3], bg [1:3] and dbg [1:3]) to allow for arbitration between the 60x processors. the 60x processors share all 60x interface signals of the tspc106, except the bus request (br ), bus grant (bg ) and the data bus grant (dbg ) signals. when an external l2 controller (or integrated l2 cache module) is used, three signals of the l2 interface change their functions (to brl2 ,bgl2 and dbgl2 )toallowthe tspc106 to arbitrate between the external cache and the 60x processor(s). memory interface the memory interface controls processor and pci interactions to main memory. it is capable of supporting a variety of dram or extended data out (edo) dram and rom or flash rom configurations as main memory. the maximum supported memory size is 1-gbyte of dram or edo dram, with 16m bytes of rom or flash rom. the memory controller of the tspc106 supports the various memory sizes through software initial- ization of on-chip configuration registers. parity or ecc is provided for error detection. the tspc106 controls the 64-bit data path to main memory (72-bit data path with parity or ecc). to reduce loading on the data bus, system designers must implement buffers between the 60x bus and memory. the tspc106 features configurable data/parity buffer control logic to accommodate several buffer types. the tspc106 is capable of supporting a variety of dram/edo configurations. dram/edo banks can be built of simms, dimms or directly-attached memory devices. thirteen multiplexed address signals provide for device densities up to 16 mbits. eight row address strobe (ras [0:7]) signals support up to eight banks of memory. the tspc106 supports bank sizes from 2m bytes to 128m bytes. eight column address strobe (cas [0:7]) signals are used to provided byte selection for memory bank access (note that all cas signals are driven in ecc mode). the tspc106 provides parity checking and generation in two forms, normal parity and read-modify-write (rmw) parity. as an alternative to simple parity, the tspc106tspc106 supports error checking and correction (ecc) for system memory. using ecc, the tspc106 detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble (i.e., four bits or one-half byte). for rom/flash support, the tspc106 provides 20 address bits (21 address bits for the 8-bit wide rom interface), two bank selects, one output enable, and one flash rom write enable. the 16-mbyte rom space is subdivided into two 8-mbyte banks. bank 0 (selected by rcs0 ) is addressed from 0xff80_0000 to 0xffff_ffff. bank 1 (selected by rcs1 ) is addressed from 0xff00_0000 to 0xff7f_ffff. a configuration signal, flash output enable (foe ) sampled at reset, determines the bus width of the rom or flash device (8-bit or 64-bit) in bank 0. the data bus width for rom bank 1 is always 64 bits. for systems using the 8-bit interface to bank 0, the rom/flash device must be connected to the most-significant byte lane of the data bus (dh[0:7]). the tspc106 also supports a mixed rom system configuration. that is, the system can have the upper 8m bytes (bank 0) of rom space located on the pci bus and the lower 8m bytes (bank 1) of rom located on the 60x/memory bus.
33 tspc106 2102b ? hirel ? 02/02 pci interface the tspc106 ? s pci interface is compliant with the pci local bus specification, revi- sion 2.1, and follows the guidelines in the pci system design guide, revision 1.0 for host bridge architecture. the pci interface connects the processor and memory buses to the pci bus, to which i/o components are connected. the pci bus uses a 32-bit mul- tiplexed address/data plus various control and error signals. the pci interface of the tspc106 functions as both a master and target device. as a master, the tspc106 supports read and write operations to the pci memory space, the pci i/o space, and the pci configuration space. the tspc106 also supports pci spe- cial-cycle and interrupt-acknowledge commands. as a target, the tspc106 supports read and write operations to system memory. mode selectable big-endian to little-endian conversion is supplied at the pci interface. internal buffers are provided for i/o operation between the pci bus and the 60x proces- sor or memory. processor read and write operations each have a 32-byte buffer and memory operation has one 32-byte read buffer and two 32-byte write buffers. system design information this section provides electrical and thermal design recommendations for successful application of the tspc106. pll configuration the tspc106 requires a single system clock input, sysclk. the sysclk frequency dictates the frequency of operation for the pci bus. an internal pll on the tspc106 generates a master clock that is used for all of the internal (core) logic. the master clock provides the core frequency reference and is phase-locked to the sysclk input. the 60x processor, l2 cache and memory interfaces operate at the core frequency. in the 5:2 clock mode (rev. 4.0 only), the tspc106 needs to sample the 60x bus clock (on the lbclaim configuration input) to resolve clock phasing with the pci bus clock (sysclk). the pll is configured by the pll[0:3] signals. for a given sysclk (pci bus) fre- quency, the clock mode configuration signals (pll[0:3]) set the core frequency (and the frequency of the vco controlling the pll lock). the supported core and vco frequen- cies and the corresponding pll[0:3] settings are provided in table 19.
34 tspc106 2102b ? hirel ? 02/02 notes: 1. pll[0:3] settings not listed are reserved. some pll configurations may select bus, cpu or vco frequencies which are not useful, not supported or not tested. see ? input ac specifications ? on page 26 for valid sysclk and vco frequencies. 2. 5:2 clock modes are only supported by tspc106 rev 4.0; earlier revisions do not support 5:2 clock modes. the 5:2 modes require a 60x bus clock applied to the 60x clock phase (lbclaim ) configuration input signal during power-on reset, hard reset and coming out of sleep and suspend power saving modes. 3. in pll-bypass mode, the sysclk input signal clocks the internal circuitry directly, the pll is disabled and the core/sysclk ratio is set for 1:1 mode operation. this mode is intended for factory use only. note: the ac timing specifications given in this document do not apply in pll-bypass mode. 4. in clock-off mode, no clocking occurs inside the tspc106 regardless of the sysclk input. 5. pll[0:3] = 0010 (1:1 core/sysclk ratio; x8 vco multiplier) exists on the chip but will fail to lock 50% of the time. there- fore this configuration should not be used and 1:1 modes between 16 and 25 mhz are not supported. pll power supply filtering the av dd power signal is provided on the 106 to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered using a circuit similar to the one shown in figure 15. the circuit should be placed as close as possible to the av dd pin to ensure it filters out as much noise as possible. figure 15. pll power supply filter circuit table 2 0. core/vco frequencies and pll settings pll[0:3](1) core/syscl ratio vco multiplier core frequency (vco frequency) in mhz pci bus 16.6 mhz pci bus 20 mhz pci bus 25 mhz pci bus 33.3 mhz 0010 1:1 x8 33.3 (266) 0101 2:1 x4 40 (160) 50 (200) 66.6 (266) 0110 5:2 (2) x2 83.3 (166) 0111 5:2 (2) x4 41.6 (166) 50 (200) 62,5 (250) 83,3 (333) 1000 3:1 x2 75 (150) 1001 3:1 x4 60 (240) 75 (300) 0011 pll bypass (3) pll off sysclk clocks core circuitry directly 1 x core/sysclk ratio implied 1111 clock off (4) pll off no core clocking occurs gnd v dd (3.3v) 10 ? 10 f0.1 f av dd
35 tspc106 2102b ? hirel ? 02/02 decoupling recommendations due to the tspc106's large address and data buses, and high operating frequencies, the tspc106 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be pre- vented from reaching other components in the system, and the tspc106 itself requires a clean, tightly regulated source of power. it is strongly recommended that the system design include six to eight 0.1 f (ceramic) and 10 f (tantalum) decoupling capacitors to provide both high- and low-frequency fil- tering. these capacitors should be placed closely around the perimeter of the tspc106 package (or on the underside of the pcb). it is also recommended that these decou- pling capacitors receive their power from separate v dd and gnd power planes in the pcb, utilizing short traces to minimize inductance. only smt (surface mount technol- ogy) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd plane, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors are 100 f (avx tps tantalum) or 330 f (avx tps tantalum). connection recommendations to ensure reliable operation, it is recommended to connect unused inputs to an appro- priate signal level. unused active low inputs should be tied (using pull-up resistors) to v dd . unused active high inputs should be tied (using pull-down resistors) to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd ,av dd and gnd pins of the tspc106. pull-up resistor recommendations the tspc106 requires pull-up (or pull-down) resistors on several control signals of the 60x and pci buses to maintain the control signals in the negated state after they have been actively negated and released by the tspc106 or other bus masters. the jtag test reset signal, trst , should be pulled down during normal system operation. also, as indicated in table 21, the factory test signal, lssd_mode ,mustbepulledupfornor- mal device operation. during inactive periods on the bus, the address and transfer attributes on the bus (a[0:31], tt[0:4], tbst ,wt ,ci and gbl ) are not driven by any master and may float in the high-impedance state for relatively long periods of time. since the tspc106 must continually monitor these signals, this float condition may cause excessive power draw by the input receivers on the tspc106 or by other receivers in the system. it is recom- mended that these signals be pulled up or restored in some manner by the system. the 60x data bus input receivers on the tspc106 do not require pull-up resistors on the data bus signals (dh[0:31], dl[0:31] and par[0:7]). however, other data bus receivers in the system may require pull-up resistors on these signals. in general, the 60x address and control signals are pulled up to 3.3 vdc and the pci control signals are pulled up to 5 vdc through weak (2 - 10 k ? ) resistors. resistor val- ues may need to be adjusted stronger to reduce induced noise on specific board designs. table 21 summarizes the pull-up/pull-down recommendations for the tspc106.
36 tspc106 2102b ? hirel ? 02/02 preparation for delivery packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. certificate of compliance atmel offers a certificate of compliance with each shipment of parts, confirming that the products are in compliance with mil-std-883 and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. handling mos devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: devices should be handled on benches with conductive and grounded surfaces. ground test equipment, tools and operator. do not handle devices by the leads. store devices in conductive foam or carriers. avoid use of plastic, rubber or silk in mos areas. maintain relative humidity above 50% if practical. table 2 1. pull-up/pull-down recommendations signal type signals pull-up/pull-down 60x bus control br n, ts ,xats ,aack , artry ,ta pull-up to 3.3v dc 60x bus address/transfer attributes a[0:31], tt[0:4], tbst ,wt ,ci ,gbl pull-up to 3.3v dc cache control ads pull-up to 3.3v dc hit, tv pull-up to 3.3v dc or pull-down to gnd depending on programmed polarity pci bus control req ,frame ,irdy , devsel ,trdy , stop , serr , perr ,lock , flshreq , isa_master pull-up to 5v dc note: for closed systems not requiring 5v power, these may be pulled up to 3.3 vdc. jtag trst pull-down to gnd (during normal system operation) factory test lssd_mode pull-up to 3.3v dc
37 tspc106 2102b ? hirel ? 02/02 package mechanical data cbga package parameters figure 16. cbga mechanical drawing table 2 2. cbga package parameters parameter min max parameter min max package outline 21 mm x 25 mm a 25.0 0.2 interconnects 303 (16 x 19 ball array minus one) b 21.0 0.2 pitch 1.27 mm c 2.3 3.16 solder attach 63/37 sn/pb d 0.82 0.93 solder balls 10/90 sn/pb, 0.89 mm diameter g 1.27 basic maximum module height 3.16 mm h 0.79 0.99 co-planarity specification 0.15 mm k 0.635 basic n5.86.0 p7.27.4 ? t ? c a1 0.200 2x 0.200 2x ? e ? ? f ? 0.150 t h g k 12345678910111213141516 w v u t r p n m l k j h g f e d c b a 303x s t s e s f s t *not to scale top view bottom view p br a n ? d ? 0.300 ? 0.150 g
38 tspc106 2102b ? hirel ? 02/02 ci_cga package parameters figure 17. ci_cga mechanical drawing table 2 3. ci-cga package parameters parameter min max parameter min max package outline 21 mm x 25 mm a 25.0 basic interconnects 303 (16 x 19 ball array minus one) b 21.0 basic pitch 1.27 mm c 3.84 basic solder attach 63/37 sn/pb d 0.79 0.99 solder balls 10/90 sn/pb, 0.89 mm diameter g 1.27 basic maximum module height 3.84 mm h 1.545 1.695 co-planarity specification 0.15 mm k 0.635 basic n 6.2 basic p 7.6 basic ? t ? c a1 0.200 2x 0.200 2x ? e ? ? f ? 0.150 t h g k 12345678910111213141516 w v u t r p n m l k j h g f e d c b a 303x s t s e s f s t *not to scale top view bottom view p br a n ? d ? 0.300 ? 0.150 g
39 tspc106 2102b ? hirel ? 02/02 ordering information note: for availability of different versions, contact your atmel sales office. ts pc106a m gs b/q 66 cg manufacturer's prefix type package g: cbga gs: ci_cga screening level (1) _: standard b/q: mil-std-883, class q b/t: according to mil-std-883 u: upscreening u/t: upscreening + burn-in revision level (1) ce: rev. 3.0 cg: rev. 4.0 operating frequency (1) 66: 66 mhz 83: 83.3 mhz temperature range: t c m: -55 c, +125 c v: -40 c, +110 c
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